For several decades CMOS device scaling has enabled integrated circuits with increased functionality which allowed many major innovations. There are however several obstacles to this continuous device scaling. The development costs of advanced technology nodes are such that only a handful of players are still involved in the scaling race. With such an increased density, the power dissipated by these advanced circuits is not sustainable.
In order to tackle these power and performance issues facing future electronic integrated circuits while maintaining the development costs at reasonable levels, scientists and engineers are working relentlessly in several directions. Among the many areas of future technology development three most significant focus areas are novel materials, new device architectures and 3D integration.
The successful integration of new materials such as high-k dielectrics in the gate stack of the MOSFET has enabled a significant boost in the device performance without further static power losses. And the search for a material (Ge, III-V, 2D TMDs…) to replace the Si channel in the MOSFET is ongoing.
Novel architecture concepts have been developed some already in production (FinFETs, FDSOI) and some still in the research phase such as tunnel FETs and non-charge based devices (spintronics).
3D monolithic integration enables further density increase per unit area without necessarily scaling the devices, it also enables the integration of different functionality on top of the logic circuit. Integrating the memory on top of the CPU for example could significantly reduce computing time and power consumption.